What we have prototyped is MC/DC (modified/condition/decision coverage) for RLL code for Rockwell controllers. Most procedural language test coverage tools do branch coverage or some such because Relay Ladder Logic typically doesn't branch, this doesn't work very well. We've experimented with test coverage tools for Rockwell Control Logix controllers.
Here is one that runs on windows supposedly: There are a couple of ladder logic editors (with simultors) available for free. Sorry, I have never looked for ladder logic to/from verilog translators.īut ladder logic in my day was only just being put into a computer for programming PLC's - most of the relay systems I used were REAL Relays, wired into the cabinets!! It may be helpful to program in some unit delays. Verilog will be an easier language to develop your tests and testbenches in! (Note: in Ladder Logic for PLC convention, Rnn is for internal relays, while, Xnn is an input and Ynn is an output, as can be quickly gleaned from one of the online tutorials.
Make sure you're testcases give good CODE coverage of your logic! And If your ladder editing software gives you decent naming capabilities, use them, rather than Rnn. Then use a free verilog simulator like Icarus to develop a testbench and test your system. Or you could use an assign statement assign R18 = R16 & (R15 | R12) Ī latching relay assign R18 = (set condition) || R18 & !(break condition) To an expression like always R18 = !R16 & ( R15 | R12) Ladder logic can be transformed to one of the modern HDL's like Verilog.
The verification of "logical" systems in the IC design arena is known as "Design Verification", which is the process of ensuring that the system you design in hardware (RTL) implements the desired functionality.